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CT2561 Bus Controller, Remote Terminal and BUS Monitor
FOR MIL-STD-1553B
Features
I I I I I I I I I I I I
Second Source Compatible to the BUS-65610 16MHz CT2565 Replacement RTU implements all dual redundant mode codes Selective mode code illegalization available 16 bit microprocessor compatibility BC checks status word for correct address and set flags RTU illegal mode codes externally selectable 16 bit Processor compatibility DMA handshaking for subsystem message transfers Continuous On-Line and Initiated Built-In-Test MIL-PRF-38534 compliant circuits available Packaging - Hermetic Metal * 78 Pin, 2.1" x 1.87" x .25" Plug-In type package * 82 Lead, 2.2" x 1.61" x .18" Flat package
CIRCUIT TECHNOLOGY
www.aeroflex.com
A E RO
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ISO 9001
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RTIFIED
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General Description
The CT2561 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller (BC), Remote Terminal Unit (RTU) and Bus Monitor (MT). Packaged in a hybrid plug-in or flatpack, the CT2561 performs all the functions required to interface a MIL-STD-1553 dual redundant serial data bus such as ACT4487 and a subsystem parallel three-state data bus. Using a single Aeroflex custom monolithic ASIC design, the CT2561 features pin-for-pin and functional CT2565 compatibility, user initiated self-test, and low power consumption. Compatible with most microprocessors the CT2561 provides a 16bit three-state parallel data bus and uses direct memory access (DMA type) handshaking for subsystem transfers. All message transfer timing, DMA and control lines are provided internally, thereby reducing the subsystem overhead associated with message transfers. The CT2561 implements all dual redundant MIL-STD-1553 mode codes. In addition, any mode code may (Optionally) be legalized through the use of an external PROM. Complete error detection is provided by the CT2561 for BC and RTU operation. Error detection includes: response time-out, inter-message gaps, sync, parity, Manchester, word count and bit count. The CT2561 is fully compliant with MIL-STD-1553, is available screened in accordance with the requirements of MIL-STD-883 and operates over the full military temperature range of -55C to +125C.
eroflex Circuit Technology - Data Bus Modules For The Future (c) SCDCT2561 REV A 8/16/99
STATUS INPUTS
Aeroflex Circuit Technology
RTADDR
DBACCEPT SSFLAG SERREQ SSERR SSBUSY
MODE CODE CONTROL CH A CONTROL REMOTE TERMINAL LOGIC
TXINH A TXDATA A TXDATA A RXDATA A RXDATA A
CH A ENCODE/ DECODE
WC0-WC4 T/R LMC ILLCMD
I/O0 - I/O16 DATA BUFFERS
DATA BUS
BUFENA
R/W
EN
2 CH B CONTROL CONTROL BUS BUS CONTROLLER LOGIC I/O BUS I/O LOGIC BUFFERS PARITY CHECKER
TXINH TXDATA TXDATA RXDATA RXDATA
B B B B B
CH B ENCODE/ DECODE
RTADDR
RTADR0 RTADR1 RTADR2 RTADR3 RTADR4 RTADRP
RTADDR
BUSREQ BUSGRNT BUSACK TIMEOUT SOM EOM INCMD CS OE WR TESTIN TESTOUT RT/BC MT BCSTART CHA/CHB LOOPERR MSGERR STATERR LWORD HSFAIL STATEN BITEN NBGRNT ADRINC NODT BSCTRCV
16MHz
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Figure 1 - CT2561 Block Diagram
Table 1A - Pin Function Table (78 Pin Plug-In)
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol RT/BC MT STATEN TIMEOUT HSFAIL DBACCEPT SSFLAG SVCREQ INCMD SSER TESTOUT WC1 WC3 TXINH B T/R CHA/CHB CS OE BUSREQ +5V DB0(LSB) DB2 DB4 DB6 DB8 DB10 DB12 DB14 I/O I I O O O I I I O I O O O O O O O O I I/O I/O I/O I/O I/O I/O I/O I/O Description Mode Select input - logic "1" for RT mode, logic "0" for BC mode. Monitor mode enable. When unit is operating as a BC, a logic "0" will select monitor mode. Output signal in RT mode that indicates status word is being transferred on the internal bus. Indicates No Response Timeout has occurred during BC and RTU (RT to RT transfer). Output in RT mode indicating the DMA transfer did not occur in time to allow proper operation on the 1553 bus. Input signal used to set DBACCEPT bit in status register for response to a valid mode command on the 1553 bus. Input which controls the SSFLAG bit in the status register. Input which controls the service request bit in the status word. Output signal indicating the RT is currently in a message transfer sequence. Input which controls the subsystem error bit in the status register. Factory test point. Do not connect. WC bit 1 - latched output of command word. WC bit 3 - latched output of command word. Transmitter inhibit output for channel B. Output indicating T/R bit of current command word in RT mode. Output indicating current selected channel (0 = Channel A). Chip Select output for subsystem memory control. Output Enable output for subsystem memory control. Output signal used to initiate transfer to/from subsystem. +5 Volt DC input. Least significant bit - 16 bit parallel data bus. Bit 2 of data bus. Bit 4 of data bus. Bit 6 of data bus. Bit 8 of data bus. Bit 10 of data bus. Bit 12 of data bus. Bit 14 of data bus.
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SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Table 1A - Pin Function Table (78 Pin Plug-In) (continued)
Pin # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol LWORD MSGERR TXDATA A RXDATA A RTADP RTAD1 RTAD3 RESET TXDATA B RXDATA B 16MHz GROUND BCSTART NBGRNT BITEN WR BUSGRNT LOOPERR SSBUSY ILLCMD ADRINC CHASSIS WC0 WC2 WC4 TXINH A LMC TESTIN I/O O O I I I I I O I I I O O O I O I I O O O O O O Description Last word output during BC mode indicates last data word of the current message transfer has been transferred on the parallel bus. Output signal which indicates an error occurred during the current message sequence. Bipolar serial data output to positive input of bus transceiver. Bipolar serial input from negative output of bus transceiver. Parity bit input for RT address. Bit 1 of RT address input. Bit 3 of RT address input. System reset input - resets all inputs in module. Bipolar serial data output to negative input bus transceiver. Bipolar serial data input from positive output of bus transceiver. 16MHz TTL clock input. Signal ground. Cycle enable input Logic "0" initiates bus controller message transfer operation. New bus grant output from RT indicates beginning of message transfer sequence. Built in Test enable output indicates RT is transferring BlT word on internal 16 bit bus. Write enable output for control of subsystem memory. Bus request input in response to DTREQ. Allows BC/RT to transfer data to subsystem. Loop error output. Logic "0" indicates failure of loop back transmitted data. Subsystem busy input for RT status word. Illegal command input to RT, used to block RT response to an illegal command. Increment output pulse. Goes LOW at the completion of each word transfer to/from subsystem. Can increment external address counter. Frame ground electricity isolated from signal ground LSB of current command word count field. Bit 2 of word count field. Bit 4 of word count field. Transmitter inhibit output signal for Channel A. Latched Mode Command. Logic "1" indicates current word command is a mode code word, WC0-WC4. Factory test point. Do not connect.
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SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Table 1A - Pin Function Table (78 Pin Plug-In) (continued)
Pin # 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Symbol EOM BUFENA BUSACK DB1 DB3 DB5 DB7 DB9 DB11 DB13 DB15(MSB) STATERR TXDATA A RXDATA A NODT RTAD0 RTAD2 RTAD4 BCSTRCV TXDATA B RXDATA B SOM I/O O I O I/O I/O I/O I/O I/O I/O I/O I/O O O I O I I I O O I O Description End of message output. Logic "0" occurs when BC/RT message is completed. Buffer enable input, may be driven LOW by STATEN or BITEN if subsystem must read bit or Status words. Enables internal 16 bit bus onto subsystem bus. Bus acknowledge output. LOW during DMA Handshake, in response to BUSGRNT. Bit 1 of 16 bit parallel bus. Bit 3 of 16 bit parallel bus. Bit 5 of 16 bit parallel bus. Bit 7 of 16 bit parallel bus. Bit 9 of 16 bit parallel bus. Bit 11 of 16 bit parallel bus. Bit 13 of 16 bit parallel bus. Bit 15 of 16 bit parallel bus. BC output indicates one or more bits set or address mismatch in a received status word. Bipolar serial data output to negative input of bus transceiver. Bipolar serial data input from positive output of bus transceiver. No data input. Logic "0" indicates the 1553 bus is idle; HIGH means device front end is active. LSB of 5 bit RT address. Bit 2 of RT address. Bit 4 of RT address. Broadcast receive. Logic "0" means the current command was a broadcast command. Bipolar serial output to positive input of bus transceiver. Bipolar serial input from negative output of bus transceiver. Start of message output indicates beginning of RT/BC message transfer sequence.
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SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Table 1B - CT2561 Pin Out Description (Plug-In)
Pin #
1 2 3
Function
RT/BC
MT STATEN TIMEOUT HSFAIL DBACCEPT SSFLAG SVCREQ INCMD SSER TESTOUT WC1 WC3 TXINH B T/R CHB/CHA CS
Pin #
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
Function
GND BCSTART NBGRNT BITEN WR BUSGRNT LOOPERR SSBUSY ILLCMD ADRINC CASE GND WC0 WC2 WC4 TXINH A LMC TESTIN EOM BUFENA BUSACK DB1 DB3 DB5 DB7 DB9 DB11 DB13 DB15 (MSB) STATERR TXDATA A RXDATA A NODT RTAD0 RTAD2 RTAD4 BCSTRCV TXDATA B RXDATA B SOM
1 41 2 42 3 43 4 44 5 45 6 46 7 47 8 48 9 49 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 20
RT/BC
BCSTART MT NBGRNT STATEN BITEN TIMEOUT WR HSFAIL BUSGRNT DBACCEPT LOOPERR SSFLAG SSBUSY SVCREQ ILLCMD INCMD ADRINC SSER CASE GND TESTOUT WC0 WC1 WC2 WC3 WC4 TXINH B TXINH A T/R LMC CHB/CHA TESTIN CS EOM
CT2561
MIL-STD-1553 BUS Controller, Remote Terminal and BUS MONITOR
OE
BUFENA BUSREQ BUSACK +5 Volt
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 (MSB) LWORD STATERR MSGERR TXDATA A TXDATA A RXDATA A RXDATA A NODT RTADP RTAD0 RTAD1 RTAD2 RTAD3 RTAD4 RESET BCSTRCV TXDATA B TXDATA B RXDATA B RXDATA B 16MHz SOM GND
21 60 22 61 23 62 24 63 25 64 26 65 27 66 28 67 29 68 30 69 31 70 32 71 33 72 34 73 35 74 36 75 37 76 38 77 39 78 40
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
OE
BUSREQ + 5 Volt DB0 (LSB) DB2 DB4 DB6 DB8 DB10 DB12 DB14 LWORD MSGERR TXDATA A RXDATA A RTADP RTAD1 RTAD3 RESET TXDATA B RXDATA B 16MHz
Plug-In Pin Connection Diagram, CT2561 and Pinout
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SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
Table 2 - CT2561 Pin Out Description (FP)
Pin #
1 2 3
Function
N/C RT/BC BCSTART MT NBGRNT STATEN BITEN TIMEOUT WR HSFAIL BUSGRNT DBACCEPT LOOPERR SSFLAG SSBUSY SVCREQ ILLCMD INCMD ADRINC SSER CASE GND TESTOUT WC0 WC1 WC2 WC2 WC4 TXINH B TXINH A T/R LMC CHB/CHA TESTIN CS EOM OE BUFENA BUSREQ BUSACK +5V N/C
Pin #
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82
Function
N/C GROUND SOM 16MHz RXDATA B RXDATA B TXDATA B TXDATA B BCSTRCV RESET RTAD4 RTAD3 RTAD2 RTAD1 RTAD0 RTADP NODT RXDATA A RXDATA A TXDATA A TXDATA A MSGERR STATERR LWORD DB15 (MSB) DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
N/C
RT/BC BCSTART MT NBGRNT STATEN BITEN TIMEOUT WR HSFAIL BUSGRNT DBACCEPT LOOPERR SSFLAG SSBUSY SVCREQ ILLCMD INCMD ADRINC SSER CASE GND TESTOUT WC0 WC1 WC2 WC3 WC4 TXINH B TXINH A T/R LMC CHB/CHA TESTIN CS EOM OE BUFENA BUSREQ BUSACK +5V N/C
N/C
CT2561FP
MIL-STD-1553 BUS Controller, Remote Terminal and BUS MONITOR
DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 (MSB) LWORD STATERR MSGERR TXDATA A TXDATA A RXDATA A RXDATA A NODT RTADP RTAD0 RTAD1 RTAD2 RTAD3 RTAD4 RESET BCSTRCV TXDATA B TXDATA B RXDATA B RXDATA B 16MHz SOM GROUND
N/C
82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
Flat Package Pin Connection Diagram, CT2561 and Pinout
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SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
2.100
1.870 Lead 1 & ESD Designator
.100 .110
Pin 1 Pin 2
1.900
.050 Pin 19 TYP Pin 20 Pin 59 Pin 41 .018 DIA TYP
.250 MAX
1.650 1.500
Pin 60 Pin 78 Pin 21 Pin 22 .100 TYP Pin 39 Pin 40
.250
1.800
Figure 2 - Plug In Package Outline
2.200 MAX .010 .002
Pin 42
.050 Pin 82
.015
.180 MAX
1.610 MAX Lead 1 & ESD Designator .400 MIN .095 (4 Places) 2.000 .050 Lead Centers 41 Leads/Side
Pin 41
.080
Figure 3 - Flat Package Outline
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SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number CT2561 CT2561-FP Screening Military Temperature, -55C to +125C, Screened to the individual test methods of MIL-STD-883 Package Plug in Flat Package
Specifications subject to change without notice
Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com/act1.htm
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Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) THE-1553 E-Mail: sales-act@aeroflex.com
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SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700

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